View MAX3301EEBA-T_725464.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-3275; Rev 2; 1/06
USB On-the-Go Transceivers and Charge Pumps
General Description
The MAX3301E/MAX3302E fully integrated USB On-theGo (OTG) transceivers and charge pumps allow mobile devices such as PDAs, cellular phones, and digital cameras to interface directly with USB peripherals and each other without the need of a host PC. Use the MAX3301E/MAX3302E with an embedded USB host to directly connect to peripherals such as printers or external hard drives. The MAX3301E/MAX3302E integrate a USB OTG transceiver, a VBUS charge pump, a linear regulator, and an I2C-compatible, 2-wire serial interface. An internal level shifter allows the MAX3301E/MAX3302E to interface with +1.65V to +3.6V logic supply voltages. The MAX3301E/MAX3302E's OTG-compliant charge pump operates with +3V to +4.5V input supply voltages, and supplies an OTG-compatible output on V BUS while sourcing more than 8mA of output current. The MAX3301E/MAX3302E enable USB OTG communication from highly integrated digital devices that cannot supply or tolerate the +5V VBUS levels that USB OTG requires. The device supports USB OTG session-request protocol (SRP) and host-negotiation protocol (HNP). The MAX3301E/MAX3302E provide built-in 15kV electrostatic-discharge (ESD) protection for the VBUS, ID_IN, D+, and D- terminals. The MAX3301E/MAX3302E are available in 25-bump chip-scale (UCSPTM), 28-pin TQFN, and 32-pin TQFN packages and operate over the extended -40C to +85C temperature range.
Features
USB 2.0-Compliant Full-/Low-Speed OTG Transceivers Ideal for USB On-the-Go, Embedded Host, or Peripheral Devices 15kV ESD Protection on ID_IN, VBUS, D+, and DTerminals Charge Pump for VBUS Signaling and Operation Down to 3V Internal VBUS and ID Comparators Internal Switchable Pullup and Pulldown Resistors for Host/Peripheral Functionality I2C Bus Interface with Command and Status Registers Linear Regulator Powers Internal Circuitry and D+/D- Pullup Resistors Support SRP and HNP
MAX3301E/MAX3302E
Ordering Information
PART MAX3301EEBA-T MAX3301EETJ MAX3302EEBA-T* MAX3302EETI PACKAGE SIZE (mm) 2.5 x 2.5 5x5 2.5 x 2.5 4x4 PINPACKAGE 25 UCSP 25 UCSP PKG CODE B25-1 B25-1
32 TQFN-EP** T3255-4 28 TQFN-EP** T2844-1
Selector Guide
PART POWER-UP STATE I2C ADDRESSES FOR SPECIAL-FUNCTION REGISTER 2
MAX3301E
Shutdown (sdwn = 1, bit 0 of specialfunction register 2) Operating (sdwn = 1, bit 0 of specialfunction register 2)
16h, 17h
Note: All devices specified over the -40C to +85C operating range. UCSP bumps are in a 5 x 5 array. The UCSP package size is 2.5mm x 2.5mm x 0.62mm. Requires solder temperature profile described in the Absolute Maximum Ratings section. UCSP reliability is integrally linked to the user's assembly methods, circuit board material and environment. See the UCSP Applications Information section of this data sheet for more information. *Future product--contact factory for availability. **EP = Exposed paddle.
MAX3302E
The
10h, 11h, and 16h, 17h
MAX3301E powers up in its lowest power state and the MAX3302E powers up in the operational, VP/VM USB mode.
Applications
Mobile Phones PDAs Digital Cameras MP3 Players
Purchase of I2C components from Maxim Integrated Products, Inc. or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. UCSP is a trademark of Maxim Integrated Products, Inc.
Pin Configurations appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
ABSOLUTE MAXIMUM RATINGS
All voltages are referenced to GND. VCC, VL .....................................................................-0.3V to +6V TRM (regulator off or supplied by VBUS) ..-0.3V to (VBUS + 0.3V) TRM (regulator supplied by VCC)...............-0.3V to (VCC + 0.3V) D+, D- (transmitter tri-stated) ...................................-0.3V to +6V D+, D- (transmitter functional)....................-0.3V to (VCC + 0.3V) VBUS .........................................................................-0.3V to +6V ID_IN, SCL, SDA.......................................................-0.3V to +6V INT, SPD, RESET, ADD, OE/INT, RCV, VP, VM, SUS, DAT_VP, SE0_VM ......................-0.3V to (VL + 0.3V) C+.............................................................-0.3V to (VBUS + 0.3V) C-................................................................-0.3V to (VCC + 0.3V) Short-Circuit Duration, VBUS to GND .........................Continuous Continuous Power Dissipation (TA = +70C) 5 x 5 UCSP (derate 12.2mW/C above +70C) ...........976mW 32-Pin TQFN (5mm x 5mm x 0.8mm) (derate 21.3mW/C above +70C).............................................................1702mW 28-Pin TQFN (4mm x 4mm x 0.8mm) (derate 20.8mW/C above +70C).............................................................1666mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C Bump Reflow Temperature (Note 1) Infrared (15s) ...............................................................+200C Vapor Phase (20s) .......................................................+215C
Note 1: The UCSP package is constructed using a unique set of packaging techniques that impose a limit on the thermal profile the device can be exposed to during board-level solder attach and rework. This limit permits only the use of the solder profiles recommended in the industry-standard specification, JEDEC 020A, paragraph 7.6, Table 3 for IR/VPR and convection reflow. Preheating is required. Hand or wave soldering is not allowed.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3V to +4.5V, VL = +1.65V to +3.6V, CFLYING = 100nF, CVBUS = 1F, ESRCVBUS = 0.1 (max), TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +3.7V, VL = +2.5V, TA = +25C.) (Note 2)
PARAMETER Supply Voltage TRM Output Voltage Logic Supply Voltage VL Supply Current VCC Operating Supply Current VCC Supply Current During FullSpeed Idle VCC Shutdown Supply Current VCC Interrupt Shutdown Supply Current VCC Suspend Supply Current LOGIC I/O RCV, DAT_VP, SE0_VM, INT, OE/INT, VP, VM Output High Voltage RCV, DAT_VP, SE0_VM, INT, OE/INT, VP, VM Output Low Voltage OE/INT, SPD, SUS, RESET, DAT_VP, SE0_VM Input High Voltage VOH IOUT = 1mA (sourcing) VL - 0.4 V ICC(SHDN) ICC(ISHDN) ID_IN floating or high USB suspend mode, ID_IN floating or high SYMBOL VCC VTRM VL IVL ICC I2C interface in steady state USB normal mode, CL = 50pF, device switching at full speed vbus_drv = 1, IVBUS = 0 vbus_drv = 0, D+ = high, D- = low 1.4 0.5 3.5 20 170 CONDITIONS MIN 3.0 3.0 1.65 TYP MAX 4.5 3.6 3.60 5 10 2 0.8 10 30 500 UNITS V V V A mA mA A A A
VOL
IOUT = 1mA (sinking)
0.4
V
VIH
2/3 x VL
V
2
_______________________________________________________________________________________
USB On-the-Go Transceivers and Charge Pumps
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3V to +4.5V, VL = +1.65V to +3.6V, CFLYING = 100nF, CVBUS = 1F, ESRCVBUS = 0.1 (max), TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +3.7V, VL = +2.5V, TA = +25C.) (Note 2)
PARAMETER OE/INT, SPD, SUS, RESET DAT_VP, SE0_VM Input Low Voltage ADD Input High Voltage ADD Input Low Voltage Input Leakage Current TRANSCEIVER SPECIFICATIONS Differential Receiver Input Sensitivity Differential Receiver CommonMode Voltage Single-Ended Receiver Input Low Voltage Single-Ended Receiver Input High Voltage Single-Ended Receiver Hysteresis Single-Ended Output Low Voltage Single-Ended Output High Voltage Off-State Leakage Current Driver Output Impedance ESD PROTECTION (VBUS, ID_IN, D+, D-) Human Body Model IEC 61000-4-2 Air-Gap Discharge IEC 61000-4-2 Contact Discharge THERMAL SHUTDOWN Thermal Shutdown Low-to-High Thermal Shutdown High-to-Low CHARGE-PUMP SPECIFICATIONS (vbus_drv = 1) VBUS Output Voltage VBUS Output Current VBUS Output Ripple VBUS IVBUS IVBUS = 8mA, CVBUS = 10F 3V < VCC < 4.5V, CVBUS = 10F, IVBUS = 8mA 4.80 8 100 5.25 V mA mV +160 +150
o o
MAX3301E/MAX3302E
SYMBOL VIL
CONDITIONS
MIN
TYP
MAX 0.4
UNITS V
VIHA VILA
2/3 x VL 1/3 x VL 1
V V A
|VD+ - VD-|
0.2 0.8 2.5 0.8 2.0 0.2
V V V V V 0.3 V V A 3.6 1 13 13 15 10 6
VILD VIHD
D+, DD+, D-
VOLD VOHD
D+, D-, RL = 1.5k from D+ or D- to 3.6V D+, D-, RL = 15k from D+ or D- to GND D+, DD+, D-, not including REXT Low steady-state drive High steady-state drive 2 2 2.8
kV kV kV C C
_______________________________________________________________________________________
3
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3V to +4.5V, VL = +1.65V to +3.6V, CFLYING = 100nF, CVBUS = 1F, ESRCVBUS = 0.1 (max), TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +3.7V, VL = +2.5V, TA = +25C.) (Note 2)
PARAMETER Switching Frequency VBUS Leakage Voltage VBUS Rise Time VBUS Pulldown Resistance VBUS Pullup Resistance VBUS Input Impedance COMPARATOR SPECIFICATIONS VBUS Valid Comparator Threshold VBUS Valid Comparator Hysteresis Session-Valid Comparator Threshold Session-End Comparator Threshold dp_hi Comparator Threshold dm_hi Comparator Threshold cr_int Pulse Width cr_int Comparator Threshold ID_IN SPECIFICATIONS ID_IN Input Voltage for Car Kit ID_IN Input Voltage for A Device ID_IN Input Voltage for B Device ID_IN Input Impedance ID_IN Input Leakage Current ID_IN Pulldown Resistance D+ Pulldown Resistor D- Pulldown Resistor D+ Pullup Resistor D- Pullup Resistor ZID_IN ID_IN = VCC id_pulldown = 1 dp_pulldown = 1 dm_pulldown = 1 dp_pullup = 1 dm_pullup = 1 14.25 14.25 1.425 1.425 0.9 x VCC 70 -1 150 15 15 1.5 1.5 100 130 +1 300 15.75 15.75 1.575 1.575 0.2 x VCC 0.8 x VCC 0.1 x VCC V V V k A k k k k 0.4 VTH-VBUS VHYS-VBUS VTHSESS_VLD
SYMBOL fSW vbus_drv = 0
CONDITIONS
MIN
TYP 390
MAX 0.2 100
UNITS kHz V ms k k V mV
CVBUS = 10F, IVBUS = 8mA, measured from 0 to +4.4V vbus_dischrg = 1, vbus_drv = 0, vbus_chrg = 0 vbus_chrg = 1, vbus_drv = 0, vbus_dischrg = 0 ZINVBUS vbus_dischrg = 0, vbus_drv = 0, vbus_chrg = 0 3.8 650 40 4.4 5 930 70 4.6 50 0.8 0.2 0.8 0.8 1.4 0.5 1.3 1.3 750 0.5
6.5 1250 100 4.8
2.0 0.8 2.0 2.0 0.6
V V V V ns V
VTHSESS_END
TERMINATING RESISTOR SPECIFICATIONS (D+, D-)
4
_______________________________________________________________________________________
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
TIMING CHARACTERISTICS
(VCC = +3V to +4.5V, VL = +1.65V to +3.6V, CFLYING = 100nF, CVBUS = 1F, ESRCVBUS = 0.1 (max), TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +3.7V, VL = +2.5V, TA = +25C.) (Note 2)
PARAMETER D+, D- Rise Time D+, D- Fall Time Rise-/Fall-Time Matching Output-Signal Crossover Voltage D+, D- Rise Time D+, D- Fall Time Rise-/Fall-Time Matching Output-Signal Crossover Voltage Driver Propagation Delay (DAT_VP, SE0_VM to D+, D-) Driver Disable Delay Driver Enable Delay VCRS_L tPLH tPHL tPDZ tPZD TRANSMITTER TIMING (FULL-SPEED MODE) Low-to-high, Figures 2 and 6 High-to-low, Figures 2 and 6 Figures 1 and 8 Figures 2 and 8 25 25 25 25 ns ns ns VCRS_F tR tF SYMBOL tR tF CONDITIONS Figures 2 and 5 Figures 2 and 5 Figures 2 and 5 (Note 3) Figures 2, 6, and 7 (Note 3) Figures 2 and 5 Figures 2 and 5 Figures 2 and 5 Figures 2, 6, and 7 MIN 4 4 90 1.3 75 75 80 1.3 TYP MAX 20 20 110 2.0 300 300 125 2.0 UNITS ns ns % V ns ns % V
TRANSMITTER CHARACTERISTICS (FULL-SPEED MODE)
TRANSMITTER CHARACTERISTICS (LOW-SPEED MODE)
TRANSMITTER TIMING (LOW-SPEED MODE) (Low-speed delay timing is dominated by the slow rise and fall times.) SPEED-INDEPENDENT TIMING CHARACTERISTICS Receiver Disable Delay Receiver Enable Delay D+ Pullup Assertion Time RCV Rise Time RCV Fall Time Differential-Receiver Propagation Delay Single-Ended-Receiver Propagation Delay Interrupt Propagation Delay VBUS_CHRG Propagation Delay Time to Exit Shutdown Shutdown Delay Dominated by the VBUS rise time 0.2 1 10 tR tF tPHL, tPLH tPHL, tPLH tPVZ tPZV Figure 4 Figure 4 During HNP Figures 3 and 5, CL = 15pF Figures 3 and 5, CL = 15pF Figures 3 and 10, |D+ - D-| to DAT_VP Figures 3 and 9, |D+ - D-| to RCV Figures 3 and 9, D+, D- to DAT_VP, SE0_VM 4 4 30 30 30 100 30 30 3 ns ns s ns ns ns ns s s s s
_______________________________________________________________________________________
5
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
I2C-/SMBusTM-COMPATIBLE TIMING SPECIFICATIONS
(VCC = +3V to +4.5V, VL = +1.65V to +3.6V, CFLYING = 100nF, CVBUS = 1F, ESRCVBUS = 0.1 (max), TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +3.7V, VL = +2.5V, TA = +25C.) (Note 2)
PARAMETER Serial Clock Frequency Bus-Free Time Between Stop and Start Conditions Start-Condition Hold Time Stop-Condition Setup Time Clock Low Period Clock High Period Data Setup Time Data Hold Time Rise Time of SDA and SCL Fall Time of SDA and SCL Capacitive Load for each Bus Line SYMBOL fSCL tBUF tHD_STA tSU_STO tLOW tHIGH tSU_DAT tHD_DAT tR tF CB (Note 4) (Note 5) Measured from 0.3 x VL to 0.7 x VL (Note 5) 20 + 0.1 x CB 1.3 0.6 0.6 1.3 0.6 100 0.9 300 300 400 CONDITIONS MIN TYP MAX 400 UNITS kHz s s s s s ns s ns ns pF
SDA AND SCL I/O STAGE CHARACTERISTICS Input-Voltage Low Input-Voltage High SDA Output-Voltage Low Pulse Width of Suppressed Spike VIL VIH VOL tSP ISINK = 3mA (Note 6) 50 0.7 x VL 0.4 0.3 x VL V V V ns
Note 2: Parameters are 100% production tested at +25C. Limits over temperature are guaranteed by design. Note 3: Guaranteed by bench characterization. Limits are not production tested. Note 4: A master device must provide a hold time of at least 300ns for the SDA signal to bridge the undefined region of SCL's falling edge. Note 5: CB is the total capacitance of one bus line in pF, tested with CB = 400pF. Note 6: Input filters on SDA, SCL, and ADD suppress noise spikes of less than 50ns.
SMBusTM is a trademark of Intel Corporation. 6 _______________________________________________________________________________________
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
Typical Operating Characteristics
(Typical operating circuit, VCC = +3.7V, VL = +2.5V, CFLYING = 100nF, TA = +25C, unless otherwise noted.)
INPUT CURRENT (ICC) vs. VBUS OUTPUT CURRENT
MAX3301E toc01
VBUS OUTPUT VOLTAGE vs. VBUS OUTPUT CURRENT
VCC = 3.0V VCC = 4.2V
MAX3301E toc02
VBUS OUTPUT VOLTAGE vs. INPUT VOLTAGE (VCC)
LINEAR REGULATOR POWERED BY VCC VBUS OUTPUT VOLTAGE (V) 5.50
MAX3301E toc03
50
VCC = 3.3V VCC = 4.2V LINEAR REGULATOR POWERED BY VCC
5.50 5.25 VBUS OUTPUT VOLTAGE (V) 5.00 4.75 4.50 4.25 4.00 LINEAR REGULATOR POWERED BY VCC 0 5 10 15 20 25
5.75
INPUT CURRENT (ICC) (mA)
40
30
5.25 IVBUS = 0 IVBUS = 8mA 4.75
20
5.00
10
0 0 4 8 12 16 20 VBUS OUTPUT CURRENT (mA)
4.50 30 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VBUS OUTPUT CURRENT (mA) INPUT VOLTAGE (VCC) (V)
TIME TO ENTER SHUTDOWN
MAX3301E toc04
TIME TO EXIT SHUTDOWN
MAX3301E toc05
VBUS DURING SRP
MAX3301E toc06
D+ 1V/div
D1V/div
VBUS 1V/div
D1V/div
D+ 1V/div
CVBUS > 13F
VBUS 1V/div SCL 2V/div SCL 1V/div CVBUS > 96F 100ns/div 4s/div 20ns/div
DRIVER PROPAGATION DELAY HIGH-TO-LOW (LOW-SPEED MODE)
MAX3301E toc07
DRIVER PROPAGATION DELAY LOW-TO-HIGH (LOW-SPEED MODE)
MAX3301E toc08
DRIVER PROPAGATION DELAY HIGH-TO-LOW (FULL-SPEED MODE)
MAX3301E toc09
DAT_VP 1V/div
DAT_VP 1V/div
DAT_VP 1V/div
D1V/div
D+ 1V/div
D1V/div
D+ 1V/div 100ns/div 100ns/div
D1V/div 4ns/div
D+ 1V/div
_______________________________________________________________________________________
7
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
Typical Operating Characteristics (continued)
(Typical operating circuit, VCC = +3.7V, VL = +2.5V, CFLYING = 100nF, TA = +25C, unless otherwise noted.)
DRIVER PROPAGATION DELAY LOW-TO-HIGH (FULL-SPEED MODE)
MAX3301E toc10
DRIVER ENABLE DELAY (FULL-SPEED MODE)
MAX3301E toc11
DRIVER DISABLE DELAY (FULL-SPEED MODE)
MAX3301E toc12
DAT_VP 1V/div
OE/INT 1V/div
OE/INT 1V/div
D+ 1V/div
D+ 1V/div
D1V/div
D1V/div 4ns/div 10ns/div
D1V/div 10ns/div
D+ 1V/div
DRIVER ENABLE DELAY (LOW-SPEED MODE)
MAX3301E toc13
DRIVER DISABLE DELAY (LOW-SPEED MODE)
MAX3301E toc14
SUPPLY CURRENT vs. TEMPERATURE
MAX3301E toc15
1.0 OE/INT 1V/div
SUPPLY CURRENT (mA)
OE/INT 1V/div
0.8
0.6
D+ 1V/div
D1V/div
VCC = 4.2V VCC = 3.3V
0.4
CD+ = CD- = 400pF 100ns/div
D1V/div 10ns/div
D+ 1V/div
0.2 VBUS OFF FULL-SPEED IDLE 0 -40 -15 10 35 60 85 TEMPERATURE (C)
8
_______________________________________________________________________________________
USB On-the-Go Transceivers and Charge Pumps
Pin Description
PIN MAX3302E 28-PIN TQFN 1 MAX3301E 32-PIN TQFN 2 UCSP NAME FUNCTION System-Side Data Input/Output. DAT_VP is an input if OE/INT is logic 0. DAT_VP is an output if OE/INT is logic 1. Program the function of DAT_VP with the dat_se0 bit (bit 2 of control register 1, see Table 7). Input Power Supply. Connect a +3V to +4.5V supply to VCC and bypass to GND with a 1F capacitor. The supply range enables direct powering from one Li+ battery. No Connection. Not internally connected. Charge-Pump Flying-Capacitor Negative Terminal System-Side Data Input/Output. SE0_VM is an input if OE/INT is logic 0. SE0_VM is an output if OE/INT is logic 1. Program the function of SE0_VM with the dat_se0 bit (bit 2 of control register 1, see Table 7). Ground I2C-Compatible Serial Data Interface. Open-drain data input/output. I2C-Compatible Serial Clock Input Output Enable. OE/INT controls the input or output status of DAT_VP/SE0_VM and D+/D-. When OE/INT is logic 0, the device is in transmit mode. When OE/INT is logic 1, the device is in receive mode. When in suspend mode, OE/INT can be programmed to function as an interrupt output that detects the same interrupts as INT. The oe_int_en bit (bit 5 of control register 1, see Table 7) enables and disables the interrupt circuitry of OE/INT. The irq_mode bit (bit 1 of special-function register 2, see Table 15) programs the output configuration of INT and OE/INT as open-drain or push-pull. D+ and D- Differential Receiver Output. In receive mode (see Table 4), when D+ is high and D- is low, RCV is high. In receive mode, when D+ is low and D- is high, RCV is low. RCV is low in suspend mode. Speed-Selector Input. Connect SPD to GND to select the low-speed data rate (1.5Mbps). Connect SPD to VL to select the full-speed data rate (12Mbps). Disable the SPD input by writing a 1 to spd_susp_ctl (bit 1 in special-function register 1, see Table 14). The speed bit (bit 0 of control register 1, see Table 7) determines the maximum data rate of the MAX3301E/MAX3302E when the SPD input is disabled. System-Side Logic-Supply Input. Connect to the system's logic-level power supply, +1.65V to +3.6V. This sets the maximum output levels of the logic outputs and the input thresholds of the logic inputs. Bypass to GND with a 0.1F capacitor. Active-High Suspend Input. Drive SUS low for normal USB operation. Drive SUS high to enable suspend mode. RCV asserts low in suspend mode. Disable the SUS input by writing a 1 to spd_susp_ctl (bit 1 in special-function register 1, see Table 14). The suspend bit (bit 1 of control register 1, see Table 7) determines the operating mode of the MAX3301E/MAX3302E when the SUS input is disabled.
MAX3301E/MAX3302E
D2
DAT_VP
2, 25
3, 29 1, 4, 9, 12, 17, 25, 28 5 6
D1, E3 -- C1 C2 B1, C5 A1 B2
VCC
3, 9, 23 4 5
N.C. CSE0_VM
6, 18 7 8
7, 21 8 10
GND SDA SCL
10
11
A2
OE/INT
11
13
A3
RCV
12
14
B3
SPD
13
15
A4
VL
14
16
A5
SUS
_______________________________________________________________________________________
9
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
Pin Description (continued)
PIN MAX3302E 28-PIN TQFN 15 MAX3301E 32-PIN TQFN 18 UCSP NAME FUNCTION Active-Low Interrupt Source. Program the INT output as push-pull or opendrain with the irq_mode bit (bit 1 of special-function register 2, see Tables 15 and 16). Active-Low Reset Input. Drive RESET low to asynchronously reset the MAX3301E/MAX3302E. I2C-Interface Address Selection Input. (See Table 5.) ID Input. ID_IN is internally pulled up to VCC. The state of ID_IN determines ID bits 3 and 5 of the interrupt source register (see Table 10). USB Differential Data Input/Output. Connect D- to the D- terminal of the USB connector through a 27.4 1% series resistor. USB Differential Data Input/Output. Connect D+ to the D+ terminal of the USB connector through a 27.4 1% series resistor. Single-Ended Receiver Output. VM functions as a receiver output in all operating modes. VM duplicates D-. USB Transceiver Regulated Output Voltage. TRM provides a regulated 3.3V output. Bypass TRM to GND with a 1F ceramic capacitor installed as close to the device as possible. TRM normally derives power from VCC. TRM provides power to internal circuitry and provides the pullup voltage for the internal USB pullup resistor. Do not use TRM to power external circuitry. The reg_sel bit (bit 3 of special-function register 2, see Table 15 and Table 16) controls the TRM power source with software. Single-Ended Receiver Output. VP functions as a receiver output in all operating modes. VP duplicates D+. USB Bus Power. Use VBUS as an output to power the USB bus, or as an input to power the internal linear regulator. Bits 5 to 7 of control register 2 (see Table 8) control the charging and discharging functions of VBUS. Charge-Pump Flying-Capacitor Positive Terminal Exposed Paddle. Connect to GND or leave floating
B4
INT
16 17 19 20 21 22
19 20 22 23 24 26
B5 C3 C4 D5 E5 D4
RESET ADD ID_IN DD+ VM
24
27
E4
TRM
26
30
D3
VP
27 28 EP
31 32 EP
E2 E1 --
VBUS C+ EP
Test Circuits and Timing Diagrams
TEST POINT 27.4 DUT D+/DCL 220 LOAD FOR DISABLE TIME (D+/D-) MEASUREMENT V = 0 FOR tPHZ. V = VTRM FOR tPLZ. CL = 50pF FOR FULL SPEED. CL = 200pF TO 600pF FOR LOW SPEED. V TEST POINT 27.4 DUT D+/D15k LOAD FOR 1) ENABLE TIME (D+/D-) MEASUREMENT 2) DAT_VP/SEO_VM TO D+/D- PROPAGATION DELAY 3) D+/D- RISE/FALL TIMES CL CL = 50pF FOR FULL SPEED. CL = 200pF TO 600pF FOR LOW SPEED.
Figure 1. Load for Disable Time Measurement
Figure 2. Load for Enable Time, Transmitter Propagation Delay, and Transmitter Rise/Fall Times
10
______________________________________________________________________________________
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
Test Circuits and Timing Diagrams (continued)
TEST POINT DUT RCV, VP, VM, DAT_VP, SEO_VM LOAD FOR 1) D+/D- TO RCV/VP/VM/DAT_VP/SEO_VM PROPAGATION DELAYS 2) RCV/VP/VM/DAT_VP/SEO_VM RISE/FALL TIMES (CL = 15pF) CL
VL OE/INT 0V VOH D+ OR DVL / 2 tPZD VL / 2 tPDZ VOHD - 0.3V
Figure 3. Load for Receiver Propagation Delay and Receiver Rise/Fall Times
TEST POINT 270 DUT DAT_VP SEO_VM
VOL
VOLD + 0.3V
Figure 8. Enable and Disable Timing
D+
3V
V = 2/3 x VL
DtPHL tPLH VL VL / 2 0V tPHL DAT_VP tPLH VL VL / 2 0V tPLH SE0_VM tPHL VL VL / 2 0V D+/D- RISE/FALL TIMES 8ns, VL = 1.8V, 2.5V, OR 3.3V RCV 0V
Figure 4. Load for DAT_VP, SE0_VM Enable/Disable Time Measurements
tR VOH tF 90%
VOL
10%
Figure 5. Rise and Fall Times
DAT_VP
tPHL
tPLH
SE0_VM
Figure 9. D+/D- to RCV, DAT_VP, SE0_VM Propagation Delays (VP_VM Mode)
D+ VOHD VCRS_F, VCRS_L D- VOLD VCRS_F, VCRS_L
D+ 3V
Figure 6. Timing of DAT_VP, SE0_VM to D+, D- in VP_VM Mode (dat_se0 = 0)
DAT_VP
DtPHL DAT_VP tPLH
0V VL VL / 2 0V
tPHL
tPLH
SE0_VM D+ VOHD VCRS_F, VCRS_L D- VOLD VCRS_F, VCRS_L
SE0_VM D+/D- RISE/FALL TIMES 8ns, VL = 1.8V, 2.5V, OR 3.3V
Figure 7. Timing of DAT_VP, SE0_VM to D+/D- in DAT_SE0 Mode (dat_se0 = 1)
Figure 10. D+/D- to DAT_VP, SE0_VM Propagation Delays (DAT_SE0 Mode) 11
______________________________________________________________________________________
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
Block Diagram
ID DETECTOR ADD INT RESET SERIAL CONTROLLER VBUS CHARGE PUMP VBUS COMPARATORS LINEAR REGULATOR SCL SDA PULLUP/PULLDOWN RESISTORS CAR KIT INTERRUPT DETECTOR
ID_IN C+ C-
VBUS
TRM
DAT_VP SE0_VM OE/INT VP VM RCV VCC VL GND SPD SUS SE DPOWER BLOCK
DIFF TX
D+ D-
LEVEL TRANSLATOR SE D+
DIFF RX
MAX3301E MAX3302E
Figure 11. Block Diagram
12
______________________________________________________________________________________
USB On-the-Go Transceivers and Charge Pumps
Detailed Description
The USB OTG specification defines a dual-role USB device that acts either as an A device or as a B device. The A device supplies power on V BUS and initially serves as the USB host. The B device serves as the initial peripheral and requires circuitry to monitor and pulse VBUS. These initial roles can be reversed using HNP. The MAX3301E/MAX3302E combine a low- and fullspeed USB transceiver with additional circuitry required by a dual-role device. The MAX3301E/MAX3302E employ flexible switching circuitry to enable the device to act as a dedicated host or peripheral USB transceiver. For example, the charge pump can be turned off and the internal regulator can be powered from VBUS for bus-powered peripheral applications. The Selector Guide shows the differences between the MAX3301E and MAX3302E. The MAX3301E powers up in its lowest power state and must be turned on by setting the sdwn bit to 0. The MAX3302E powers up in the operational, VP/VM USB mode. This allows a microprocessor (P) to use the USB port for power-on bootup, without having to access I2C. To put the MAX3302E into low-power shutdown, set the sdwn bit to 0. In the MAX3302E, special-function register 2 can be addressed at I2C register location 10h, 11h (as well as locations 16h, 17h) to support USB OTG serial-interface engine (SIE) implementations that are limited to I2C register addresses between 0h and 15h. accordance with USB OTG specifications. The charge pump can be turned off to conserve power when not used. Control of the charge pump is set through the vbus_drv bit (bit 5) of control register 2 (see Table 8).
MAX3301E/MAX3302E
Linear Regulator (TRM)
An internal 3.3V linear regulator powers the transceiver and the internal 1.5k D+/D- pullup resistor. Under the control of internal register bits, the linear regulator can be powered from VCC or VBUS. The regulator power-supply settings are controlled by the reg_sel bit (bit 3) in specialfunction register 2 (Tables 15 and 16). This flexibility allows the system designer to configure the MAX3301E/ MAX3302E for virtually any USB power situation. The output of the TRM is not a power supply. Do not use as a power source for any external circuitry. Connect a 1.0F (or greater) ceramic or plastic capacitor from TRM to GND, as close to the device as possible.
VBUS Level-Detection Comparators Comparators drive interrupt source register bits 0, 1, and 7 (Table 10) to indicate important USB OTG VBUS voltage levels: * VBUS is valid (vbus_vld)
* * USB session is valid (sess_vld) USB session has ended (sess_end)
Transceiver
The MAX3301E/MAX3302E transceiver complies with the USB version 2.0 specification, and operates at fullspeed (12Mbps) and low-speed (1.5Mbps) data rates. Set the data rate with the SPD input. Set the direction of data transfer with the OE/INT input. Alternatively, control transceiver operation with control register 1 (Table 7) and special-function registers 1 and 2 (see Tables 14, 15, and 16).
The vbus_valid comparator sets vbus_vld to 1 if VBUS is higher than the VBUS valid comparator threshold. The VBUS valid status bit (vbus_vld) is used by the A device to determine if the B device is sinking too much current (i.e., is not supported). The session_valid comparator sets sess_vld to 1 if VBUS is higher than the session valid comparator threshold. This status bit indicates that a data transfer session is valid. The session_end comparator sets sess_end to 1 if VBUS is higher than the
Level Shifters
Internal level shifters allow the system-side interface to run at logic-supply voltages as low as +1.65V. Interface logic signals are referenced to the voltage applied to the logic-supply voltage, VL.
VBUS VBUS_VLD VTH-VBUS
Charge Pump
The MAX3301E/MAX3302E's OTG-compliant charge pump operates with +3V to +4.5V input supply voltages (VCC) and supplies a +4.8V to +5.25V OTG-compatible output on VBUS while sourcing the 8mA or greater output current that an A device is required to supply. Connect a 0.1F flying capacitor between C+ and C-. Bypass VBUS to GND with a 1F to 6.5F capacitor, in
SESS_VLD VTH-SESS_VLD
SESS_END VTH-SESS_END
Figure 12. Comparator Network Diagram 13
______________________________________________________________________________________
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
session end comparator threshold. Figure 12 shows the level-detector comparators. The interrupt-enable registers (Tables 12 and 13) determine whether a falling or rising edge of VBUS asserts these status bits. * * * Discharge VBUS through a resistor Provide power-on or receive power from VBUS Charge VBUS through a resistor
ID_IN
The USB OTG specification defines an ID input that determines which dual-role device is the default host. An OTG cable connects ID to ground in the connector of one end and is left unconnected in the other end. Whichever dual-role device receives the grounded end becomes the A device. The MAX3301E/MAX3302E provide an internal pullup resistor on ID_IN. Internal comparators detect if ID_IN is grounded or left floating.
Interrupt Logic
When OTG events require action, the MAX3301E/ MAX3302E provide an interrupt output signal on INT. Alternatively, OE/INT can be configured to act as an interrupt output while the device operates in USB suspend mode. Program INT and OE/INT as open-drain or push-pull interrupts with irq_mode (bit 1 of special-function register 2, see Tables 15 and 16).
VBUS Power Control VBUS is a dual-function port that powers the USB bus and/or provides a power source for the internal linear regulator. The VBUS power-control block performs the various switching functions required by an OTG dual-role device. These actions are programmed by the system logic using bits 5 to 7 of control register 2 (see Table 8) to:
The OTG supplement allows an A device to turn VBUS off when the bus is not being used to conserve power. The B device can issue a request that a new session be started using SRP. The B device must discharge VBUS to a level below the session-end threshold (0.8V) to ensure that no session is in progress before initiating SRP. Setting bit 6 of control register 2 to 1, discharges VBUS to GND through a 5k current-limiting resistor. When VBUS has discharged, the resistor is removed from the circuit by resetting bit 6 of control register 2. An OTG A device is required to supply power on VBUS. The MAX3301E/MAX3302E provide power to VBUS from VCC or from the internal charge pump. Set bit 5 in control register 2 to 1 in both cases. Bit 5 in control register 2 controls a current-limited switch, preventing damage to the device in the event of a VBUS short circuit. An OTG B device (peripheral mode) can request a session using SRP. One of the steps in implementing SRP requires pulsing VBUS high for a controlled time. A 930 resistor limits the current according to the OTG specification. Pulse VBUS through the pullup resistor by asserting bit 7 of control register 2. Prior to pulsing VBUS (bit 7), a B device first connects an internal pulldown resistor to discharge VBUS below the session-end threshold. The discharge current is limited by the 5k resistor and set by bit 6 of control register 2. An OTG A device must
Table 1. Functional Blocks Enabled During Specific Operating Modes
MODE Shutdown1 Interrupt Shutdown2 Suspend3 Normal Operating I2C ID_IN X sess_end COMP X X sess _vld COMP X vbus_ vld COMP X X cr_int COMP X X dp_hi COMP X dm_hi COMP X TRM X X TX X X DIFF RX X X X SE RX X X
= Enabled. X = Disabled. 1. For the MAX3301E, enter shutdown mode by writing a 1 to sdwn (bit 0 of special-function register 2). For the MAX3302E, enter shutdown mode by writing a 0 to sdwn (bit 0 of special-function register 2). 2. Enter interrupt shutdown mode by writing a 1 to int_sdwn (bit 0 of special-function register 1). 3. Enter suspend mode by writing a 1 to spd_susp_ctl (bit 1 of special-function register 1) and suspend (bit 1 of control register 1), or by writing a 0 to spd_susp_ctl (bit 1 of special-function register 1) and driving SUS high.
14
______________________________________________________________________________________
USB On-the-Go Transceivers and Charge Pumps
supply 5V power and at least 8mA on VBUS. Setting bit 5 of control register 2 turns on the VBUS charge pump. this mode, OE/INT detects the same interrupts as INT. Set irq_mode (bit 1 in special-function register 2, see Tables 15 and 16) to 0 to program OE/INT as an opendrain interrupt output. Set irq_mode to 1 to configure OE/INT as a push-pull interrupt output. RCV RCV monitors D+ and D- when receiving data. RCV is a logic 1 for D+ high and D- low. RCV is a logic 0 for D+ low and D- high. RCV retains its last valid state when D+ and D- are both low (single-ended zero, or SE0). RCV asserts low in suspend mode. Table 4 shows the state of RCV. SPD Use hardware or software to control the slew rate of the D+ and D- terminals. The SPD input sets the slew rate of the MAX3301E/MAX3302E when spd_susp_ctl (bit 1 in special-function register 1, see Table 14) is 0. Drive SPD low to select low-speed mode (1.5Mbps). Drive SPD high to select full-speed mode (12Mbps). Alternatively, when spd_susp_ctl (bit 1 of special-function register 1) is 1, software controls the slew rate. The SPD input is ignored when using software to control the data rate. The speed bit (bit 0 of control register 1, see Table 7) sets the slew rate when spd_susp_ctl = 1. SUS Use hardware or software to control the suspend mode of the MAX3301E/MAX3302E. Set spd_susp_ctl (bit 1 of special-function register 1, see Table 14) to 0 to allow the SUS input to enable and disable the suspend mode of the MAX3301E/MAX3302E. Drive SUS low for normal operation. Drive SUS high to enable suspend mode. RCV asserts low in suspend mode while all other circuitry remains active. Alternatively, when the spd_susp_ctl bit (bit 1 of specialfunction register 1) is set to 1, software controls the suspend mode. Set the suspend bit (bit 1 of control register 1, see Table 7) to 1 to enable suspend mode. Set the suspend bit to 0 to resume normal operation. The SUS input is ignored when using software to control suspend mode. The MAX3301E/MAX3302E must be in full-speed mode (SPD = high or speed = 1) to issue a remote wake-up from the device when in suspend mode.
MAX3301E/MAX3302E
Operating Modes
The MAX3301E/MAX3302E have four operating modes to optimize power consumption. Only the I2C interface remains active in shutdown mode, reducing supply current to 1A. The I2C interface, the ID_IN port, and the session-valid comparator all remain active in interrupt shutdown mode. RCV asserts low in suspend mode; however, all other circuitry remains active. Table 1 lists the active blocks' power in each of the operating modes.
Applications Information
Data Transfer
Transmitting Data to the USB The MAX3301E/MAX3302E transceiver features two modes of transmission: DAT_SE0 or VP_VM (see Table 3). Set the transmitting mode with dat_se0 (bit 2 in control register 1, see Table 7). In DAT_SE0 mode with OE/INT low, DAT_VP specifies data for the differential transceiver, and SE0_VM forces D+/D- to the single-ended zero (SE0) state. In VP_VM mode with OE/INT low, DAT_VP drives D+, and SE0_VM drives D-. The differential receiver determines the state of RCV. Receiving Data from the USB The MAX3301E/MAX3302E transceiver features two modes of receiving data: DAT_SE0 or VP_VM (see Table 4). Set the receiving mode with dat_se0 (bit 2 in control register 1, see Table 7). In DAT_SE0 mode with OE/INT high, DAT_VP is the output of the differential receiver and SE0_VM indicates that D+ and D- are both logic-low. In VP_VM mode with OE/INT high, DAT_VP provides the input logic level of D+ and SE0_VM provides the input logic level of D-. The differential receiver determines the state of RCV. VP and VM echo D+ and D-, respectively.
OE/INT OE/INT controls the direction of communication. OE/INT can also be programmed to act as an interrupt output when in suspend mode. The output-enable portion controls the input or output status of DAT_VP/SE0_VM and D+/D-. When OE/INT is a logic 0, DAT_VP and SE0_VM function as inputs to the D+ and D- outputs in a method depending on the status of dat_se0 (bit 2 in control register 1). When OE/INT is a logic 1, DAT_VP and SE0_VM indicate the activity of D+ and D-.
OE/INT functions as an interrupt output when the MAX3301E/MAX3302E is in suspend mode and oe_int_en = 1 (bit 5 in control register 1, see Table 7). In
RESET The active-low RESET input allows the MAX3301E/ MAX3302E to be asynchronously reset without cycling the power supply. Drive RESET low to reset the internal registers (see Tables 7-16 for the default power-up states). Drive RESET high for normal operation.
______________________________________________________________________________________
15
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
2-Wire I2C-Compatible Serial Interface
A register file controls the various internal switches and operating modes of the MAX3301E/MAX3302E through a simple 2-wire interface operating at clock rates up to 400kHz. This interface supports data bursting, where multiple data phases can follow a single address phase.
Table 2. Setting the Direction of Data Transfer in General-Purpose Buffer Mode
dplus_dir 0 0 1 1 dminus_ dir 0 1 0 1 DIRECTION OF DATA TRANSFER DAT_VP D+ SE0_VM DDAT_VP D+ SE0_VM DDAT_VP D+ SE0_VM DDAT_VP D+ SE0_VM D-
UART Mode
Set uart_en (bit 6 in control register 1) to 1 to place the MAX3301E/MAX3302E in UART mode. D+ transfers data to DAT_VP and SE0_VM transfers data to D- in UART mode. General-Purpose Buffer Mode Set gp_en (bit 7 in special-function register 1) and dat_se0 (bit 2 in control register 1) to 1, set uart_en (bit 6 in control register 1) to 0, and drive OE/INT low to place the MAX3301E/MAX3302E in general-purpose buffer mode. Control the direction of data transfer with dminus_dir and dplus_dir (bits 3 and 4 of special-function register 1, see Tables 2 and 14). Serial Addressing The MAX3301E/MAX3302E operate as a slave device that sends and receives control and status signals through an I2C-compatible 2-wire interface. The interface uses a serial data line (SDA) and a serial clock line (SCL) to achieve bidirectional communication between master(s) and slave(s). A master (typically a microcontroller) initiates all data transfers to and from the MAX3301E/MAX3302E and generates the SCL clock that synchronizes the data transfer (Figure 13). The MAX3301E/MAX3302E SDA line operates as both an input and as an open-drain output. SDA requires a
pullup resistor, typically 4.7k. The MAX3301E/ MAX3302E SCL line only operates as an input. SCL requires a pullup resistor if there are multiple masters on the 2-wire interface, or if the master in a single-master system has an open-drain SCL output. Each transmission consists of a start condition (see Figure 14) sent by a master device, the MAX3301E/ MAX3302E 7-bit slave address (determined by the state of ADD), plus an R/W bit (see Figure 15), a register address byte, one or more data bytes, and a stop condition (see Figure 14).
SDA tSU: DAT tLOW SCL tHIGH tHD: STA tR START CONDITION tF REPEATED START CONDITION STOP START CONDITION CONDITION tHD: DAT tSU: STA tHD: STA tSU: STO tBUF
Figure 13. 2-Wire Serial-Interface Timing Details
16
______________________________________________________________________________________
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
Table 3. Transmit Mode
MODE CONTROL PIN/BIT SUS 0 Functional DAT_SE0 0 0 0 0 Functional VP_VM 0 0 0 1 1 1 1 Suspend 1 1 1 1 1 Receiving Generalpurpose buffer 0 GP_EN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OE/INT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 DAT_SE0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 X X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X INPUT DAT_VP SE0_VM 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X X 0 1 0 0 0 1 0 1 0 1 0 0 0 1 0 1 Driver is Hi-Z Driver is Hi-Z OUTPUT D+ D1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 Driver is Hi-Z Driver is See Table 4 Hi-Z General-purpose buffer mode USB suspend mode USB functional mode transceiver and I2C interface are fully functional DESCRIPTION
X
1
0
1
See Table 2
SDA
SCL
S
P STOP CONDITION
START CONDITION
Figure 14. Start and Stop Conditions
SDA START SCL
1
0
0
1
0
0
A0
R/W
ACK
MSB
LSB
Figure 15. Slave Address ______________________________________________________________________________________ 17
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
Table 4. Receive Mode
CONTROL PIN/BIT MODE SUS (NOTE 7) 0 0 0 Functional DAT_SE0 0 1 1 1 1 0 0 0 Functional VP_VM 0 1 1 1 1 Generalpurpose buffer Transmitting (see Table 3) Unidirectional (transmitter only) X GP_EN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 OE/INT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X DAT_SE0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 X INPUTS BI_DI D+ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DAT_VP Last value of DAT_VP 1 0 Undefined 0 1 0 1 0 1 0 1 0 1 0 1 See Table 2 OUTPUTS SE0_VM 1 0 0 0 1 0 0 0 0 0 1 1 0 0 1 1 RCV Last value of RCV 1 0 Undefined 0 0 0 0 Last value of RCV 1 0 Undefined 0 0 0 0 0 Echo D+ Echo DVP VM
X
X
0
X
X
--
0
X
X
X
X
0
--
0
Note 7: Enter suspend mode by driving SUS high or by writing a 1 to suspend (bit 1 in control register 1), depending on the status of spd_susp_ctl in special-function register 1. X = Don't care.
18
______________________________________________________________________________________
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
Start and Stop Conditions Both SCL and SDA assert high when the interface is not busy. A master device signals the beginning of a transmission with a start (S) condition by transitioning SDA from high to low while SCL is high. The master issues a stop (P) condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission (see Figure 14). Bit Transfer One data bit is transferred during each clock pulse. The data on SDA must remain stable while SCL is high (see Figure 16). Acknowledge The acknowledge bit (ACK) is the 9th bit attached to any 8-bit data word. ACK is always generated by the receiving device. The MAX3301E/MAX3302E generate an ACK when receiving an address or data by pulling SDA low during the ninth clock period. When transmitting data, the MAX3301E/MAX3302E wait for the receiving device to generate an ACK. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time.
Slave Address
A bus master initiates communication with a slave device by issuing a START condition followed by the 7bit slave address (see Figure 15). When idle, the MAX3301E/MAX3302E wait for a START condition followed by its slave address. The LSB of the address word is the read/write (R/W) bit. R/W indicates whether the master is writing to or reading from the MAX3301E/MAX3302E (R/W = 0 selects the write condition, R/W = 1 selects the read condition). After receiving the proper address, the MAX3301E/ MAX3302E issue an ACK. The MAX3301E/MAX3302E have two possible addresses (see Table 5). Address bits A6 through A1 are preset, while a reset condition or an I2C general call address loads the value of A0 from ADD. Connect ADD to GND to set A0 to 0. Connect ADD to VL to set A0 to 1. This allows up to two MAX3301E's or two MAX3302E's to share the same bus.
SDA
SCL
DATA LINE STABLE, CHANGE OF DATA DATA VALID ALLOWED
Figure 16. Bit Transfer
START CONDITION
Write Byte Format
Writing data to the MAX3301E/MAX3302E requires the transmission of at least 3 bytes. The first byte consists of the MAX3301E/MAX3302E's 7-bit slave address, followed by a 0 (R/W bit). The second byte determines which register is to be written to. The third byte is the new data for the selected register. Subsequent bytes are data for sequential registers. Figure 18 shows the typical write byte format.
CLOCK PULSE FOR ACKNOWLEDGEMENT
SCL
1
2
8
9
SDA BY TRANSMITTER S SDA BY RECEIVER
Read Byte Format
Reading data from the MAX3301E/MAX3302E requires the transmission of at least 3 bytes. The first byte consists of the MAX3301E/MAX3302E's slave address, followed by a 0 (R/W bit). The second byte selects the register from which data is read. The third byte consists
Figure 17. Acknowledge
S A6 A5
SLAVE ADDRESS (7 BITS) A4 A3 A2 A1 A0
R/W 0
A MSB
REGISTER ADDRESS (8 BITS) LSB
A MSB
DATA (8 BITS) LSB
A
P
Figure 18. Write Byte Format ______________________________________________________________________________________ 19
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
SLAVE ADDRESS (7 BITS) A6 A5 A4 A3 A2 A1 A0 REGISTER ADDRESS (8 BITS) MSB LSB
S
R/W 0
A 0
A 0
RS A6 A5
SLAVE ADDRESS (7 BITS) A4 A3 A2 A1 A0
R/W 1
A 0 MSB
DATA (8 BITS) LSB
NA 1
P 0
Figure 19. Read Byte Format R/W: Read/write (R/W = 1: read; R/W = 0: write) S: Start condition RS: Repeated start condition P: Stop condition
S A6 A5 SLAVE ADDRESS (7 BITS) A4 A3 A2 A1 A0 R/W 0 A MSB REGISTER ADDRESS (K) (8 BITS) LSB A MSB DATA (K) (8 BITS) LSB A
A: Acknowledge bit from the slave NA: Not-acknowledged bit from the master Blank: Master transmission
DATA (K+1) (8 BITS) MSB LSB
A MSB
DATA (K+2) (8 BITS) LSB
A MSB
DATA (K+N) (8 BITS) LSB
A
P
MAX3301E/MAX3302E RECOGNIZES ITS ADDRESS
MAX3301E/MAX3302E SENDS AN ACK
S A6 A5
SLAVE ADDRESS (7 BITS) A4 A3 A2 A1 A0
R/W 0
A MSB
UNSUPPORTED REGISTER ADDRESS (K) (8 BITS) LSB
A MSB
DATA (K) (8 BITS) LSB
NA
MAX3301E/MAX3302E RECOGNIZES A WRITE TO AN UNSUPPORTED LOCATION, THEN SENDS A NACK
Figure 20. Burst-Mode Write Byte Format
of the MAX3301E/MAX3302E's slave address, followed by a 1 (R/W bit). The master then reads one or more bytes of data. Figure 19 shows the typical read byte format.
Burst-Mode Write Byte Format
The MAX3301E/MAX3302E allow a master device to write to sequential registers without repeatedly sending the slave address and register address each time. The master first sends the slave address, followed by a 0 to write data to the MAX3301E/MAX3302E. The MAX3301E/MAX3302E send an acknowledge bit back to the master. The master sends the 8-bit register
address and the MAX3301E/MAX3302E return an acknowledge bit. The master writes a data byte to the selected register and receives an acknowledge bit if a supported register address has been chosen. The register address increments and is ready for the master to send the next data byte. The MAX3301E/MAX3302E send an acknowledge bit after each data byte. If an unsupported register is selected, the MAX3301E/ MAX3302E send a NACK to the master and the register index does not increment (see Figure 20).
20
______________________________________________________________________________________
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
SLAVE ADDRESS (7 BITS) A6 A5 A4 A3 A2 A1 A0 REGISTER ADDRESS (K) (8 BITS) MSB LSB
S
R/W 0
A
A
P
S A6 A5
SLAVE ADDRESS (7 BITS) A4 A3 A2 A1 A0
R/W 1
A MSB
DATA (K) (8 BITS) LSB
A MSB
DATA (K+1) (8 BITS) LSB
A
DATA (K+2) (8 BITS) MSB LSB
A MSB
DATA (K+3) (8 BITS) LSB
A MSB
DATA (K+N) (8 BITS) LSB
NA
P
MAX3301E/MAX3302E RECOGNIZE THEIR ADDRESS
MAX3301E/MAX3302E SENDS AN ACK
S A6 A5
SLAVE ADDRESS (7 BITS) A4 A3 A2 A1 A0
R/W 0
A MSB
UNSUPPORTED REGISTER ADDRESS (K) (8 BITS) LSB
A
P
S A6 A5
SLAVE ADDRESS (7 BITS) A4 A3 A2 A1 A0
R/W 1
A MSB
UNSUPPORTED REGISTER ADDRESS (K) (8 BITS) -- ALL 0's RETURNED LSB
A
ACK FROM MASTER
Figure 21. Burst-Mode Read Byte Format
Table 5. I2C Slave Address Map
ADD INPUT GND (0) VL (1) ADDRESS BITS A6 0 0 A5 1 1 A4 0 0 A3 1 1 A2 1 1 A1 0 0 A0 0 1
______________________________________________________________________________________
21
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
Table 6. Register Map
REGISTER Vendor ID Product ID Control 1 Control 2 Interrupt source Unused* Interrupt latch Interrupt-enable Falling edge Interrupt-enable Rising edge Unused*/Special Function 2 Special function 1 Revision ID Special function 2 Unused* MEMORY ADDRESS 00h, 01h 02h, 03h 04h (set) 05h (clear) 06h (set) 07h (clear) 08h (read) 09h 0Ah (set) 0Bh (clear) 0Ch (set) 0Dh (clear) 0Eh (set) 0Fh (clear) 10h (set) 11h (clear) 12h (set) 13h (clear) 14h, 15h 16h (set) 17h (clear) 18h-Fh DESCRIPTION Read only. The contents of registers 00h and 01h are 6Ah and 0Bh, respectively. Read only. The contents of registers 02h and 03h are 01h and 33h, respectively. Sets operating modes, maximum data rate, and direction of data transfer. Controls D+/D- pullup/pulldown resistor connections, ID_IN state, and VBUS behavior. Read only. Not used. Indicates which interrupts have occurred. Enables interrupts for high-to-low transitions. Enables interrupts for low-to-high transitions. MAX3301E: Not used. MAX3302E: Alternate register addresses for special-function register 2. This register is also accessible from 16h and 17h. Enables hardware/software control of the MAX3301E's behavior, interrupt activity, and operating modes. Read only. The contents of registers 14h and 15h are 77h and 41h, respectively. Sets operating modes, INT output configuration, D+/D- behavior in audio mode, and TRM source. Not used.
*When writing to an unused register, the device generates a NACK and the register index does not increment.
Burst-Mode Read Byte Format
The MAX3301E/MAX3302E allow a master device to read data from sequential registers with the burst-mode read byte protocol (see Figure 21). The master device first sends the slave address, followed by a 0. The MAX3301E/MAX3302E then sends an acknowledge bit. Next, the master sends the register address to the MAX3301E/MAX3302E, which then generates another acknowledge bit. The master then sends a stop (P) condition to the MAX3301E/MAX3302E. Next, the master sends a start condition, followed by the MAX3301E/ MAX3302E's slave address, and then a 1 to indicate a read command. The MAX3301E/MAX3302E then sends data to the master device, one byte at a time. The master sends an acknowledge bit to the MAX3301E/ MAX3302E after each data byte, and the register address of the MAX3301E/MAX3302E increments after each byte. This continues until the master sends a stop (P) condition. If
22
an unsupported register address is encountered, the MAX3301E/MAX3302E send a byte of zeros.
Registers
Control Registers There are two read/write control registers. Control register 1 (Table 7) sets operating modes, sets the data rate, and controls the direction of data transfer. Control register 2 (Table 8) connects the D+/D- pullup or pulldown resistors, sets the VBUS charge/discharge conditions, and grounds ID_IN. The control registers have two addresses that implement write-one-set and write-oneclear features for each of these registers. Writing a 1 to the set address sets that bit to 1. Writing a 1 to the clear address resets that bit to 0. Writing a 0 to either address has no effect on the bits.
______________________________________________________________________________________
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
Table 7. Control Register 1 Description (Write to Address 04h to Set, Write to Address 05h to Clear)
BIT NUMBER 0 1 2 3 4 SYMBOL speed suspend dat_se0 -- OPERATION Set to 0 for low-speed (1.5Mbps) mode. Set to 1 for full-speed (12Mbps) mode. This bit changes the data rate only if spd_susp_ctl = 1 in special-function register 1. Set to 0 for normal operating mode. Set to 1 for suspend mode. This bit changes the operating mode only if spd_susp_ctl = 1 in special-function register 1. Set to 0 for VP_VM USB mode. Set to 1 for DAT_SE0 USB mode. Not used. VALUE AT POWER-UP 0 0 0 0 0
Enables the transceiver (when configured as an A device) to connect its pullup bdis_acon_en resistor if the B device disconnect is detected during HNP. Set to 0 to disable this feature. Set to 1 to enable this feature. oe_int_en uart_en -- Set to 0 to disable the interrupt output circuitry of OE/INT. Set to 1 to enable the interrupt output circuitry of OE/INT. Set to 0 to disable UART mode. Set to 1 to enable UART mode. This bit overrides the settings of dminus_dir, dplus_dir, and gp_en bits. Not used.
5 6 7
0 0 0
Table 8. Control Register 2 Description (Write to Address 06h to Set, Write to Address 07h to Clear)
BIT NUMBER 0 1 2 3 4 5 6 7 SYMBOL dp_pullup dm_pullup dp_pulldown dm_pulldown id_pulldown vbus_drv vbus_dischrg vbus_chrg OPERATION Set to 0 to disconnect the pullup resistor to D+. Set to 1 to connect the pullup resistor to D+. Set to 0 to disconnect the pullup resistor to D-. Set to 1 to connect the pullup resistor to D-. Set to 0 to disconnect the pulldown resistor to D+. Set to 1 to connect the pulldown resistor to D+. Set to 0 to disconnect the pulldown resistor to D-. Set to 1 to connect the pulldown resistor to D-. Set to 0 to allow ID_IN to float. Set to 1 to connect ID_IN to GND. Set to 0 to turn VBUS off. Set to 1 to drive VBUS through a low impedance (see Note 8). Set to 0 to disconnect the VBUS discharge resistor. Set to 1 to connect the VBUS discharge resistor (see Note 8). Set to 0 to disconnect the VBUS charge resistor. Set to 1 to connect the VBUS charge resistor (see Note 8). VALUE AT POWER-UP 0 0 1 1 0 0 0 0
Note 8: To prevent a high-current state where the transceiver is both sourcing current to VBUS and sinking current from VBUS, the following logic is used to set bits 5, 6, and 7 of control register 2: * * * Setting vbus_drv clears vbus_dischrg and vbus_chrg Setting vbus_dischrg clears vbus_drv and vbus_chrg, unless vbus_drv is set with the same command, in which case vbus_drv clears the other bits Setting vbus_chrg clears vbus_drv and vbus_dischrg, unless either of these bits are set with the same command, as shown in Table 9 ______________________________________________________________________________________ 23
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
Table 9. VBUS Control Logic
SET COMMAND (ADDRESS 06h) vbus_drv 1 0 0 0 vbus_dischrg X 1 0 0 vbus_chrg X X 1 0 1 0 0 Not affected BEHAVIOR OF MAX3301E/MAX3302E vbus_drv vbus_dischrg 0 1 0 Not affected vbus_chrg 0 0 1 Not affected
X = Don't care.
Table 10. Interrupt Source Register (Address 08h is Read Only)
BIT NUMBER 0 1 2 3 4 5 6 7 SYMBOL vbus_vld sess_vld dp_hi id_gnd dm_hi id_float bdis_acon cr_int_sess_end CONTENTS Logic 1 if VBUS > VBUS valid comparator threshold. Logic 1 if VBUS > session valid comparator threshold. Logic 1 if VD+ > dp_hi comparator threshold (D+ assertion during data line pulsing through SRP method). Logic 1 if VID_IN < 0.1 x VCC. Logic 1 if VD- > dm_hi comparator threshold (D- assertion during data line pulsing through SRP method). Logic 1 if VID_IN > 0.9 x VCC. Logic 1 if bdis_acon_en = 1 and the MAX3301E/MAX3302E assert dp_pullup after detecting a B device disconnect during HNP. Logic 1 if VBUS < sess_end comparator threshold, or if VD+ > cr_int comparator threshold (0.4V to 0.6V), depending on the value of int_source (bit 5 of special-function register 1, see Table 14).
Interrupt Registers Four registers control all interrupt behavior of the MAX3301E/MAX3302E. A source register (Table 10) indicates the current status of the various interrupt sources. An interrupt latch register (Table 11) indicates which interrupts have occurred. An interrupt-enable low and interrupt-enable high register enable interrupts on rising or falling (or both) transitions. Tables 10-13 provide the bit configurations for the various interrupt registers. The interrupt latch, interrupt-enable low, and interrupt-enable high registers have two addresses that implement write- one-set and write-one-clear features for each of these registers. Writing a 1 to the set address sets that bit to 1. Writing a 1 to the clear address resets that bit to 0. Writing a 0 to either address has no effect on the bits. Special-Function Registers Tables 14, 15, and 16 describe the special-function registers. The special-function registers have two addresses that implement write-one-set and write-oneclear features for each of these registers. Writing a 1 to
24
the set address sets that bit to 1. Writing a 1 to the clear address resets that bit to 0. Writing a 0 to either address has no effect on the bits. Special-function register 1 determines whether hardware or software controls the maximum data rate and suspend behavior, sets the direction of data transfer, and toggles generalpurpose buffer mode. Special-function register 2 enables shutdown mode, configures the interrupt output as open-drain or push-pull, sets the TRM power source, and controls the D+/D- connections for audio mode. Table 15 depicts the special-function register 2 for the MAX3301E and Table 16 depicts the specialfunction register 2 for the MAX3302E. The MAX3301E powers up in its lowest power state and must be turned on by setting the sdwn bit to 0. The MAX3302E powers up in the operational, VP/VM USB mode. This allows a P to use the USB port for poweron boot-up, without having to access I2C. To put the MAX3302E into low-power shutdown, set the sdwn bit to 0. The MAX3302E also has special-function register 2 mapped to two I 2 C register addresses. In the MAX3302E, special-function register 2 can be
______________________________________________________________________________________
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
Table 11. Interrupt Latch Register Description (Write to Address 0Ah to Set, Write to Address 0Bh to Clear)
BIT NUMBER 0 1 2 3 4 5 6 7 SYMBOL vbus_vld sess_vld dp_hi id_gnd dm_hi id_float bdis_acon cr_int_sess_end CONTENTS vbus_vld asserts if a transition occurs on this condition and the appropriate interrupt-high or interrupt-low enable bit is set. See Tables 10, 12, and 13. sess_vld asserts if a transition occurs on this condition and the appropriate interrupt-high or interrupt-low enable bit is set. See Tables 10, 12, and 13. dp_hi asserts if a transition occurs on this condition and the appropriate interrupthigh or interrupt-low enable bit is set. See Tables 10, 12, and 13. id_gnd asserts if a transition occurs on this condition and the appropriate interrupthigh or interrupt-low enable bit is set. See Tables 10, 12, and 13. dm_hi asserts if a transition occurs on this condition and the appropriate interrupthigh or interrupt-low enable bit is set. See Tables 10, 12, and 13. id_float asserts if a transition occurs on this condition and the appropriate interrupthigh or interrupt-low enable bit is set. See Tables 10, 12, and 13. bdis_acon asserts if a transition occurs on this condition and the appropriate interrupt-high or interrupt-low enable bit is set. See Tables 10, 12, and 13. cr_int_sess_end asserts if a transition occurs on this condition and the appropriate interrupt-high or interrupt-low enable bit is set. See Tables 10, 12, and 13. VALUE AT POWER-UP 0 0 0 0 0 0 0 0
Table 12. Interrupt-Enable Low Register (Write to Address 0Ch to Set, Write to Address 0Dh to Clear)
BIT NUMBER 0 1 2 3 4 5 6 SYMBOL vbus_vld sess_vld dp_hi id_gnd dm_hi id_float bdis_acon CONTENTS Set to 0 to disable the vbus_vld interrupt for a high-to-low transition. Set to 1 to enable the vbus_vld interrupt for a high-to-low transition. See Tables 10 and 11. Set to 0 to disable the sess_vld interrupt for a high-to-low transition. Set to 1 to enable the sess_vld interrupt for a high-to-low transition. See Tables 10 and 11. Set to 0 to disable the dp_hi interrupt for a high-to-low transition. Set to 1 to enable the dp_hi interrupt for a high-to-low transition. See Tables 10 and 11. Set to 0 to disable the id_gnd interrupt for a high-to-low transition. Set to 1 to enable the id_gnd interrupt for a high-to-low transition. See Tables 10 and 11. Set to 0 to disable the dm_hi interrupt for a high-to-low transition. Set to 1 to enable the dm_hi interrupt for a high-to-low transition. See Tables 10 and 11. Set to 0 to disable the id_float interrupt for a high-to-low transition. Set to 1 to enable the id_float interrupt for a high-to-low transition. See Tables 10 and 11. Set to 0 to disable the bdis_acon interrupt for a high-to-low transition. Set to 1 to enable the bdis_acon interrupt for a high-to-low transition. See Tables 10 and 11. Set to 0 to disable the cr_int_sess_end interrupt for a high-to-low transition. Set to 1 to enable the cr_int_sess_end interrupt for a high-to-low transition. See Tables 10 and 11. VALUE AT POWER-UP 0 0 0 0 0 0 0
7
cr_int_sess_end
0
______________________________________________________________________________________
25
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
Table 13. Interrupt-Enable High Register (Write to Address 0Eh to Set, Write to Address 0Fh to Clear)
BIT NUMBER 0 1 2 3 4 5 6 SYMBOL vbus_vld sess_vld dp_hi id_gnd dm_hi id_float bdis_acon CONTENTS Set to 0 to disable the vbus_vld interrupt for a low-to-high transition. Set to 1 to enable the vbus_vld interrupt for a low-to-high transition. See Tables 10 and 11. Set to 0 to disable the sess_vld interrupt for a low-to-high transition. Set to 1 to enable the sess_vld interrupt for a low-to-high transition. See Tables 10 and 11. Set to 0 to disable the dp_hi interrupt for a low-to-high transition. Set to 1 to enable the dp_hi interrupt for a low-to-high transition. See Tables 10 and 11. Set to 0 to disable the id_gnd interrupt for a low-to-high transition. Set to 1 to enable the id_gnd interrupt for a low-to-high transition. See Tables 10 and 11. Set to 0 to disable the dm_hi interrupt for a low-to-high transition. Set to 1 to enable the dm_hi interrupt for a low-to-high transition. See Tables 10 and 11. Set to 0 to disable the id_float interrupt for a low-to-high transition. Set to 1 to enable the id_float interrupt for a low-to-high transition. See Tables 10 and 11. Set to 0 to disable the bdis_acon interrupt for a low-to-high transition. Set to 1 to enable the bdis_acon interrupt for a low-to-high transition. See Tables 10 and 11. Set to 0 to disable the cr_int_sess_end interrupt for a low-to-high transition. Set to 1 to enable the cr_int_sess_end interrupt for a low-to-high transition. See Tables 10 and 11. VALUE AT POWER-UP 0 0 0 0 0 0 0
7
cr_int_sess_end
0
addressed at I2C register location 10h, 11h (as well as locations 16h, 17h) to support USB OTG SIE implementations that are limited to I 2 C register addresses between 0h and 15h. ID and Manufacturer Register Address Map Table 17 provides the contents of the ID registers of the MAX3301E/MAX3302E. Addresses 00h and 01h comprise the vendor ID registers. Addresses 02h and 03h comprise the product ID registers. Addresses 14h and 15h comprise the revision ID registers.
External Components
External Resistors Two external resistors (27.4 1%) are required for USB connection. Install one resistor in series between D+ of the MAX3301E/MAX3302E and D+ of the USB connector. Install the other resistor in series between Dof the MAX3301E/MAX3302E and D- of the USB connector (see the Typical Operating Circuit). External Capacitors Five external capacitors are recommended for proper operation. Install all capacitors as close to the device as possible. Decouple VL to GND with a 0.1F ceramic capacitor. Bypass V CC to GND with a 1F ceramic capacitor. Bypass TRM to GND with a 1F (or greater) ceramic or plastic capacitor. Connect a 100nF flying capacitor between C+ and C- for the charge pump (see the Typical Operating Circuit). Bypass VBUS to GND with a 1F to 6.5F ceramic capacitor in accordance with USB OTG specifications. ESD Protection To protect the MAX3301E/MAX3302E against ESD, D+, D-, ID_IN, and VBUS, have extra protection against static electricity to protect the device up to 15kV. The ESD structures withstand high ESD in all states; normal oper-
Audio Car Kit
Many cell phones are required to interface to car kits. Depending upon the car kit, the interface to the phone may be required to support any or all of the following functions: * Audio input * * * Audio output Charging Control and status
D+ and D- of the MAX3301E/MAX3302E go to a highimpedance state when in shutdown mode, allowing external signals (including audio) to be multiplexed onto these lines.
26
______________________________________________________________________________________
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
Table 14. Special-Function Register 1 (Write to Address 12h to Set, Write to Address 13h to Clear)
BIT NUMBER 0 SYMBOL int_sdwn CONTENTS Set to 0 for normal operation. Set to 1 to enter interrupt shutdown mode. The I2C interface and interrupt sources remain active, while all other circuitry is off. Set to 0 to control the MAX3301E/MAX3302E behavior with SPD and SUS. Set to 1 to control the MAX3301E/MAX3302E behavior with the speed and suspend bits in control register 1 (see Table 7). Set to 0 to transfer data from DAT_VP and SE0_VM to D+ and D-, respectively. DAT_VP and SE0_VM are always inputs when this bit is 0. Set to 1 to control the direction of data transfer with OE/INT. Set to 0 to transfer data from SE0_VM to D-. Set to 1 to transfer data from D- to SE0_VM. Ensure that gp_en = 1, dat_se0 = 1, uart_en = 0, and OE/INT = low to activate this function. Set to 0 to transfer data from DAT_VP to D+. Set to 1 to transfer data from D+ to DAT_VP. Ensure that gp_en = 1, dat_se0 = 1, uart_en = 0, and OE/INT = low to activate this function. Set to 0 to use cr_int as the interrupt source for bit 7 of the interrupt source register. Set to 1 to use sess_end as the interrupt source for bit 7 of the interrupt source register (see Table 10). Session end comparator status (read only). Sess_end = 0 when VBUS > sess_end threshold. Sess_end = 1 when VBUS < sess_end threshold. Set to 0 to disable general-purpose buffer mode. Set to 1 to enable generalpurpose buffer mode. VALUE AT POWER-UP 0
1
spd_susp_ctl
0
2
bi_di
1
3
dminus_dir
0
4
dplus_dir
0
5
int_source
0
6 7
sess_end gp_en
-- 0
Note: sess_end value at power-up is dependent on the voltage at VBUS.
Table 15. MAX3301E Special-Function Register 2 (Write to Address 16h to Set, Write to Address 17h to Clear)
BIT NUMBER 0 1 2 3 4-7 SYMBOL sdwn irq_mode xcvr_input_disc reg_sel -- CONTENTS Set to 0 for normal operation. Set to 1 to enable shutdown mode. Only the I2C interface remains active in shutdown. Set to 0 to set INT and OE/INT as open-drain outputs. Set to 1 to set INT and OE/INT as push-pull outputs. Set to 0 to leave the D+/D- single-ended receiver inputs connected. Set to 1 to disconnect the D+/D- receiver inputs to reduce power consumption in audio mode. Set to 0 to power TRM from VCC. Set to 1 to power TRM from VBUS. Reserved. Set to 0 for normal operation. VALUE AT POWER-UP 1 0 0 0 0000
ation, suspend mode, interrupt shutdown, and shutdown. For the ESD structures to work correctly, connect a 1F or greater capacitor from TRM to GND and from VBUS to GND. ESD protection can be tested in various ways; the D+, D-, ID_IN, and VBUS inputs/outputs are characterized for protection to the following limits:
* * *
15kV using the Human Body Model 6kV using the IEC 61000-4-2 Contact Discharge Method 10kV using the IEC 61000-4-2 Air-Gap Discharge Method
______________________________________________________________________________________
27
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
Table 16. MAX3302E Special-Function Register 2 (Write to Address 10h or 16h to Set, Write to Address 11h or 17h to Clear)
BIT NUMBER 0 1 2 3 4-7 SYMBOL sdwn irq_mode xcvr_input_disc reg_sel -- CONTENTS Set to 0 to enable shutdown mode. Set to 1 for normal operation. Only the I2C interface remains active in shutdown. Set to 0 to set INT and OE/INT as open-drain outputs. Set to 1 to set INT and OE/INT as push-pull outputs. Set to 0 to leave the D+/D- single-ended receiver inputs connected. Set to 1 to disconnect the D+/D- receiver inputs to reduce power consumption in audio mode. Set to 0 to power TRM from VCC. Set to 1 to power TRM from VBUS. Reserved. Set to 0 for normal operation. VALUE AT POWER-UP 1 0 0 0 0000
Table 17. ID Registers
REGISTER Vendor ID Product ID Revision ID ADDRESS 00h 01h 02h 03h 14h 15h CONTENTS 6Ah 0Bh 01h 33h 77h 41h
test involves approaching the device with a charged probe. The contact discharge method connects the probe to the device before the probe is energized. Figure 25 shows the IEC 61000-4-2 current waveform. Layout Considerations The MAX3301E/MAX3302E high operating frequency makes proper layout important to ensure stability and maintain the output voltage under all loads. For best performance, minimize the distance between the bypass capacitors and the MAX3301E/MAX3302E. Use symmetric trace geometry from D+ and D- to the USB connector.
ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, methodology, and results. Human Body Model Figure 22 shows the Human Body Model and Figure 23 shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest, which is then discharged into the test device through a 1.5k resistor. IEC 61000-4-2 The IEC 61000-4-2 standard covers ESD testing and performance of finished equipment; it does not specifically refer to integrated circuits. The MAX3301E/ MAX3302E helps the user design equipment that meets level 3 of IEC 61000-4-2, without the need for additional ESD-protection components. The major difference between tests done using the Human Body Model and IEC 61000-4-2 is a higher peak current in IEC 61000-4-2, due to the fact that series resistance is lower in the IEC 61000-4-2 model. Hence, the ESD-withstand voltage measured to IEC 61000-4-2 is generally lower than that measured using the Human Body Model. Figure 24 shows the IEC 61000-4-2 model. The Air-Gap Discharge
28
UCSP Applications Information
For the latest application details on UCSP construction, dimensions, tape carrier information, PC board techniques, bump-pad layout, and the recommended reflow temperature profile, as well as the latest information on reliability testing results, refer to the Application Note: UCSP--A Wafer-Level Chip-Scale Package available on Maxim's website at www.maxim-ic.com/ucsp.
______________________________________________________________________________________
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
RC 1M CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE RD 1.5k DISCHARGE RESISTANCE DEVICE UNDER TEST
I 100% 90%
Figure 22. Human Body ESD Test Modes
10% t 30ns 60ns
IP 100% 90% AMPERES 36.8% 10% 0 0 tRL TIME
Ir
PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE)
tR = 0.7ns TO 1ns
Figure 25. IEC 61000-4-2 Current Waveform
IPEAK
Cs 100pF
STORAGE CAPACITOR
Chip Information
PROCESS: BiCMOS
tDL CURRENT WAVEFORM
Figure 23. Human Body Model Current Waveform
RC 50M to 100M CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE
RD 330 DISCHARGE RESISTANCE DEVICE UNDER TEST
Cs 150pF
STORAGE CAPACITOR
Figure 24. IEC 61000-4-2 ESD Test Model
______________________________________________________________________________________
29
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
Pin Configurations
RESET
TOP VIEW
ID_IN GND ADD D+ D-
BOTTOM VIEW
N.C. INT
MAX3301E/MAX3302E
24
N.C. VM TRM N.C. VCC VP VBUS C+
23
22
21
20
19
18
17 SDA 16 15 14 13
SUS VL SPD RCV N.C. OE/INT SCL N.C.
E 1 2 3 4 5 D C+ VBUS VCC TRM D+ C VCC DAT_VP VP VM DB CSE0_VM ADD ID_IN GND A
25 26 27 28
OE/INT
RCV
VL
SUS
GND
SCL
SPD
INT
RESET
MAX3301E
29 30 31 32 1
N.C. EXPOSED PADDLE
12 11 10 9 2
DAT_VP
3
VCC
4
N.C.
5
C-
6
SE0_VM
7
GND
8
SDA
TQFN (5mm x 5mm)
ID_IN RESET GND ADD
UCSP (2.5mm x 2.5mm)
INT 15 14 13 12 SUS VL SPD RCV OE/INT N.C. SCL 11 10 9 8 7 SDA
TOP VIEW
D+ 21 VM 22 N.C. 23 TRM 24 VCC 25 VP 26 VBUS 27 C+ 28 1 DAT_VP 2 VCC 20 D-
19
18
17
16
MAX3302E
EXPOSED PADDLE
3 N.C.
4 C-
5 SE0_VM
6 GND
TQFN (4mm x 4mm)
30
______________________________________________________________________________________
USB On-the-Go Transceivers and Charge Pumps
Typical Operating Circuit
VL VCC
MAX3301E/MAX3302E
0.1F
1F *USB OTG SPECIFICATIONS LIMIT THE TOTAL CAPACITANCE ON VBUS FROM 1F (MIN) TO 6.5F (MAX) FOR A DUAL-ROLE DEVICE. VBUS CVBUS* 4.7F 27.4 D+
VL(I/O) DAT_VP SE0_VM RCV VP VM OEV/INT ASIC INT RESET SUS SPD SDA SCL ADD
VL
VCC
VBUS D+ DID GND
MAX3301E MAX3302E
27.4 DID_IN C+ CFLYING 0.1F C-
OTG CONNECTOR
TRM GND 1F
______________________________________________________________________________________
31
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QFN THIN.EPS
L
D2 D D/2 MARKING k L E/2 E2/2 E (NE-1) X e
C L C L
b D2/2
0.10 M C A B
AAAAA
E2
PIN # 1 I.D.
DETAIL A
e (ND-1) X e
e/2
PIN # 1 I.D. 0.35x45 DETAIL B
e
L1
L
C L
C L
L
e 0.10 C A 0.08 C
e
C
A1 A3
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
I
1
2
32
______________________________________________________________________________________
USB On-the-Go Transceivers and Charge Pumps
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX3301E/MAX3302E
COMMON DIMENSIONS
PKG. 16L 5x5 20L 5x5 28L 5x5 32L 5x5 40L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
EXPOSED PAD VARIATIONS PKG. CODES T1655-2 T1655-3 T1655N-1 T2055-3
D2
3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30 3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.40 3.00 3.00 3.00 3.00 3.00 3.15 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3 3.00 3 3.00 3.00 3.00 3.20
E2
exceptions
L
A A1 A3 b D E e k L
MIN. NOM. MAX. MIN. NOM. MAX. 0.15
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.65 BSC. 0.50 BSC. 0.40 BSC. 0.50 BSC. 0.80 BSC.
DOWN BONDS ALLOWED
- 0.25 - 0.25 - 0.25 0.35 0.45 0.25 - 0.25 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60 L1 - 0.30 0.40 0.50 40 N 20 28 32 16 ND 10 4 5 7 8 10 5 7 8 4 NE ----WHHC WHHD-1 WHHD-2 WHHB JEDEC
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP.
3.00 3.00 3.00 3.00 3.00 T2055-4 T2055-5 3.15 T2855-3 3.15 T2855-4 2.60 T2855-5 2.60 3.15 T2855-6 T2855-7 2.60 T2855-8 3.15 T2855N-1 3.15 T3255-3 3.00 T3255-4 3.00 T3255-5 3.00 T3255N-1 3.00 T4055-1 3.20
3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30
3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.40
** ** ** ** ** 0.40 ** ** ** ** ** 0.40 ** ** ** ** ** **
YES NO NO YES NO YES YES YES NO NO YES YES NO YES NO YES NO YES
** SEE COMMON DIMENSIONS TABLE
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. 13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", 0.05.
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
I
2
2
______________________________________________________________________________________
33
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
24L QFN THIN.EPS
PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
E
1
2
PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
E
2
2
34
______________________________________________________________________________________
USB On-the-Go Transceivers and Charge Pumps MAX3301E/MAX3302E
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 5x5 UCSP 21-0096 H
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 35 (c) 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
25L, UCSP.EPS

▲Up To Search▲

Price & Availability of MAX3301EEBA-T

	To Download MAX3301EEBA-T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .